Intel JS28F256P30T2 TSOP(56) Device

Adapters for Automated Programmers

6th Gen	7th Gen	9th Gen
FXASM56TE, FASM56TE, FASM56T	FX4ASM56TE, FXASM56TE, FASM56TE, FASM56T, LX4ASM56TE (repl.)	LX4ASM56TE

Adapters for Manual Programmers

6th Gen	7th Gen	9th Gen
FXSM56TE, FSM56TE, FSM56TB, FXASM56TE, FASM56TE, FASM56T, FSM56T (obs.)	FX4SM56TE, FXSM56TE, FSM56TE, FSM56TB, FX4ASM56TE, FXASM56TE, FASM56TE, FASM56T, FSM56T (obs.), LX4ASM56TE (repl.)	LX4ASM56TE

Adapters for Engineering Programmers

6th Gen	7th Gen
FXSM56TE, FSM56TE, FSM56TB, FXASM56TE, FASM56TE, FASM56T, FSM56T (obs.)	FX4SM56TE, FXSM56TE, FSM56TE, FSM56TB, FX4ASM56TE, FXASM56TE, FASM56TE, FASM56T, FSM56T (obs.), LX4ASM56TE (repl.)

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Last Updated: 05/18/2023

IMPORTANT: 256Mbit (16M x 16) Intel StrataFlash(R) Memory. This device contains 17 128-bit Protection Registers PR0 through PR16 located at address range [2000000h-200010Fh] in the Data Pattern. Example: PR0[0x81-0x88] is located at [2000000h-200000Fh] PR1[0x8A-0x91] at [2000010h-200001Fh] and so on. PR0[63:0] are permanently programmed by Intel with a unique number for each flash device. PR0[127:64] and PR1 through PR16 are one-time programmable (OTP) and available for the user to program. Once programmed the user-programmable register can be locked to prevent further programming using Device > Configure menu. Once the protection register is locked the entire user segment is locked and no more user bits may be programmed. One Time Protection is available in 3 different customer ordered options. The option information is only available on the packaging of the device and is not marked on the device itself. Device operation will fail ‘Initialize’ under the following conditions: 1.’Simple OTP’ or ‘Device OTP’ option is selected under Device > Configure for a ‘Standard OTP’ device. 2.’Standard OTP’ option is selected under Device > Configure for a ‘Simple OTP’ or ‘Device OTP’ device. The first option-‘Standard OTP’ does not allow any special OTP protection of the main array. The second option-‘Simple OTP’ allows up to 512KB of Main Memory OTP protection. This option pre-defines 512KB of the main array that includes the 4×32 KB parameter blocks ganged together as one block and the adjacent 3×128 KB main blocks. Please set the bit according to the main block needed to be protected under Device > Configure:

Lock Register 0	Block Protected
Bit 2	Blocks 258:255(parameters)
Bit 3	Block 254(main)
Bit 4	Block 253(main)
Bit 5	Block 252(main)
Bit 6	Lock Bits 2-5

The third option-‘Device OTP’ will allow protection of data in all of the main memory array blocks.

OTP Address(1)	Data Pattern Address	Main Array Blocks Protected
ECh	20000D5h-20000D4h	240:258(2)
EDh	20000D7h-20000D6h	224:239
F0h	20000DDh-20000DCh	208:223
F1h	20000DFh-20000DEh	192:207
F4h	20000E5h-20000E4h	176:191
F5h	20000E7h-20000E6h	160:175
F8h	20000EDh-20000ECh	144:159
F9h	20000EFh-20000EEh	128:143
FCh	20000F5h-20000F4h	112:127
FDh	20000F7h-20000F6h	96:111
100h	20000FDh-20000FCh	80:95
101h	20000FFh-20000FEh	64:79
104h	2000105h-2000104h	48:63
105h	2000107h-2000106h	32:47
108h	200010Dh-200010Ch	16:31
109h	200010Fh-200010Eh	0:15

Notes: 1. For Top Boot the highest number OTP bit locks the lowest numbered block.For example programming bit 15 of OTP address F1h permanently locks Block 192and bit 0 permanently locks Block 207. 2. Programming bit 0 of Device Address ECh (Data Pattern Address 20000D4h) locks four parameter blocks(Blocks 255-258).
The default Device Range is set to [000000h-FFFFFFh]. Please select ‘Entire File’ under Device > Range if Protection Registers need to be included. Password Access Feature is currently not supported. ‘