Intel PC28F256P33B (Full Array Lock) BGA(64) Device

Adapters for Automated Programmers

6th Gen	7th Gen	9th Gen
FXASMR64EBGI, FXASM64EBGI, FASMR64EBGI, FASM64EBGI, FXASM64EBGC, FXASM64EBGA, FASM64EBGC, FASM64EBGA	FX4ASMR64EBGI, FX4ASM64EBGI, FXASMR64EBGI, FXASM64EBGI, FASMR64EBGI, FASM64EBGI, FXASM64EBGC, FXASM64EBGA, FASM64EBGC, FASM64EBGA, WX4ASM64EBGI (repl.), LX4ASMR64EBGI (repl.)	WX4ASM64EBGI, LX4ASMR64EBGI

Adapters for Manual Programmers

6th Gen	7th Gen	9th Gen
FXSMR64EBGI, FXSM64EBGI, FSMR64EBGI, FSM64EBGI, FXSM64EBGC, FXSM64EBGA, FSM64EBGC, FSM64EBGA, FXASMR64EBGI, FXASM64EBGI, FASMR64EBGI, FASM64EBGI, FXASM64EBGC, FXASM64EBGA, FASM64EBGC, FASM64EBGA	FX4SMR64EBGI, FX4SM64EBGI, FXSMR64EBGI, FXSM64EBGI, FSMR64EBGI, FSM64EBGI, FXSM64EBGC, FXSM64EBGA, FSM64EBGC, FSM64EBGA, FX4ASMR64EBGI, FX4ASM64EBGI, FXASMR64EBGI, FXASM64EBGI, FASMR64EBGI, FASM64EBGI, FXASM64EBGC, FXASM64EBGA, FASM64EBGC, FASM64EBGA, WX4ASM64EBGI (repl.), LX4ASMR64EBGI (repl.)	WX4ASM64EBGI, LX4ASMR64EBGI

Adapters for Engineering Programmers

6th Gen	7th Gen
FXSMR64EBGI, FXSM64EBGI, FSMR64EBGI, FSM64EBGI, FXSM64EBGC, FXSM64EBGA, FSM64EBGC, FSM64EBGA, FXASMR64EBGI, FXASM64EBGI, FASMR64EBGI, FASM64EBGI, FXASM64EBGC, FXASM64EBGA, FASM64EBGC, FASM64EBGA	FX4SMR64EBGI, FX4SM64EBGI, FXSMR64EBGI, FXSM64EBGI, FSMR64EBGI, FSM64EBGI, FXSM64EBGC, FXSM64EBGA, FSM64EBGC, FSM64EBGA, FX4ASMR64EBGI, FX4ASM64EBGI, FXASMR64EBGI, FXASM64EBGI, FASMR64EBGI, FASM64EBGI, FXASM64EBGC, FXASM64EBGA, FASM64EBGC, FASM64EBGA, WX4ASM64EBGI (repl.), LX4ASMR64EBGI (repl.)

Last Updated: 05/18/2023

If the device is not yet supported by your BPM programmer (Generation), request Device Support

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Note

IMPORTANT: 256Mbit (16M x 16) Intel StrataFlash(R) Memory. This device contains 17 128-bit Protection Registers PR0 through PR16 located at address range [2000000h-200010Fh] in the Data Pattern. Example: PR0[0x81-0x88] is located at [2000000h-200000Fh] PR1[0x8A-0x91] at [2000010h-200001Fh] and so on. PR0[63:0] are permanently programmed by Intel with a unique number for each flash device. PR0[127:64] and PR1 through PR16 are one-time programmable (OTP) and available for the user to program. Once programmed the user-programmable register can be locked to prevent further programming using Device > Configure menu. Once the protection register is locked the entire user segment is locked and no more user bits may be programmed. One Time Protection is available in 3 different customer ordered options. The option information is only available on the packaging of the device and is not marked on the device itself. This Algorithm is only for the device with FAL(Full Array Protection Locking) security feature and will allow protection of data in all of the main memory array blocks.

OTP Address⁽¹⁾	Data Pattern Address	Main Array Blocks Protected
ECh	20000D5h-20000D4h	18:0⁽²⁾
EDh	20000D7h-20000D6h	34:19
F0h	20000DDh-20000DCh	50:35
F1h	20000DFh-20000DEh	66:51
F4h	20000E5h-20000E4h	82:67
F5h	20000E7h-20000E6h	98:83
F8h	20000EDh-20000ECh	114:99
F9h	20000EFh-20000EEh	130:115
FCh	20000F5h-20000F4h	146:131
FDh	20000F7h-20000F6h	162:147
100h	20000FDh-20000FCh	178:163
101h	20000FFh-20000FEh	194:179
104h	2000105h-2000104h	210:195
105h	2000107h-2000106h	226:211
108h	200010Dh-200010Ch	242:227
109h	200010Fh-200010Eh	258:243

Notes: 1. For Bottom Boot the highest number OTP bit locks the highest numbered block.For example programming bit 15 of OTP address F1h permanently locks Block 66and bit 0 permanently locks Block 51. 2. Programming bit 0 of Device Address ECh (Data Pattern Address 20000D4h) locks four parameter blocks(Blocks 0-3). The default Device Range is set to [000000h-FFFFFFh]. Please select ‘Entire File’ under Device > Range if Protection Registers need to be included. ‘

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Additional information

Manufacturer	Intel
Packages	BGA(64)
Part Number	PC28F256P33B
Set programming	Yes
Vcc(program)	3.3
Package