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Microchip Technology PIC24F16KA102-I/ML QFN(28) Device

Adapters for Automated Programmers

6th Gen 7th Gen 9th Gen
FASMC28MLFY FX4ASMC28MLFY, FASMC28MLFY, LX4ASMC28MLFY (repl.) LX4ASMC28MLFY

Adapters for Manual Programmers

6th Gen 7th Gen 9th Gen
FSMC28MLFY, FASMC28MLFY FX4SMC28MLFY, FSMC28MLFY, FX4ASMC28MLFY, FASMC28MLFY, LX4ASMC28MLFY (repl.) LX4ASMC28MLFY

Adapters for Engineering Programmers

6th Gen 7th Gen
FSMC28MLFY, FASMC28MLFY FX4SMC28MLFY, FSMC28MLFY, FX4ASMC28MLFY, FASMC28MLFY, LX4ASMC28MLFY (repl.)

Last Updated: 05/18/2023

If the device is not yet supported by your BPM programmer (Generation), request Device Support

Note


IMPORTANT: Microcontroller with User Flash Code Memory (5.5Kx24-bit) and on-chip EEPROM (256 words) The Code Memory is a 24-bit memory addressed from [0h-57FEh] in the Data Pattern. The Code Memory is a 24-bit value on a 32-bit boundary. This algorithm assumes Little Endian format for programming data. The EEPROM is located at Buffer addresses [7FFE00h-7FFFFFh]. The Configuration bytes are located at Buffer addresses [1F00000h-1F0001Fh]. Configuration bytes are an 8-bit value on a 32-bit boundary. The Configuration bytes may be set from Device Configure or from the above mentioned addresses in the Data Pattern. All unimplemented bit locations must be set to zeros. Please use help notes in Device->Configure for more information about bit identities and reserved bit locations or see Microchip specifications. The Sum’ command generates the checksum calculation as specified by Microchip. This algorithm does not support BOOT SEGMENT CONFIGURATION REGISTER(FBS) at address F80000h. This register have default value 000Fh.

BPM does not sell programmable devices, nor do we program devices directly. BPM makes programmers and accessories to make programming in-house fast, easy, and profitable.

Additional information

Manufacturer

Microchip Technology

Packages

QFN(28)

Part Number

PIC24F16KA102-I/ML

Vcc(program)

3.3

Package