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Freescale Semiconductor MC9S12XEG384VAL(CPU Memory Map) QFP(112) Device

Adapters for Automated Programmers

6th Gen 7th Gen
FASMR112LQFA FX2ASMR112LQFA, FASMR112LQFA

Adapters for Manual Programmers

6th Gen 7th Gen
FSMR112LQFA, FASMR112LQFA FX2SMR112LQFA, FSMR112LQFA, FX2ASMR112LQFA, FASMR112LQFA, LX2ASMR112LQFA (repl.)

Adapters for Engineering Programmers

6th Gen 7th Gen
FSMR112LQFA, FASMR112LQFA FX2SMR112LQFA, FSMR112LQFA, FX2ASMR112LQFA, FASMR112LQFA, LX2ASMR112LQFA (repl.)

Last Updated: 05/18/2023

If the device is not yet supported by your BPM programmer (Generation), request Device Support

Note


IMPORTANT: The following describes the Data Pattern setup: 32K D-Flash. Actual size depends on Partition setup (if used) under Device > Configure. Dflash setup: EPAGE 00: 0x000800 TO 0x000BFF EPAGE 01: 0x010800 TO 0x010BFF EPAGE 02: 0x020800 TO 0x020BFF EPAGE 03: 0x030800 TO 0x030BFF EPAGE 04: 0x040800 TO 0x040BFF EPAGE 05: 0x050800 TO 0x050BFF EPAGE 06: 0x060800 TO 0x060BFF EPAGE 07: 0x070800 TO 0x070BFF EPAGE 08: 0x080800 TO 0x080BFF EPAGE 09: 0x090800 TO 0x090BFF EPAGE 0A: 0x0A0800 TO 0x0A0BFF EPAGE 0B: 0x0B0800 TO 0x0B0BFF EPAGE 0C: 0x0C0800 TO 0x0C0BFF EPAGE 0D: 0x0D0800 TO 0x0D0BFF EPAGE 0E: 0x0E0800 TO 0x0E0BFF EPAGE 0F: 0x0F0800 TO 0x0F0BFF EPAGE 10: 0x100800 TO 0x100BFF EPAGE 11: 0x110800 TO 0x110BFF EPAGE 12: 0x120800 TO 0x120BFF EPAGE 13: 0x130800 TO 0x130BFF EPAGE 14: 0x140800 TO 0x140BFF EPAGE 15: 0x150800 TO 0x150BFF EPAGE 16: 0x160800 TO 0x160BFF EPAGE 17: 0x170800 TO 0x170BFF EPAGE 18: 0x180800 TO 0x180BFF EPAGE 19: 0x190800 TO 0x190BFF EPAGE 1A: 0x1A0800 TO 0x1A0BFF EPAGE 1B: 0x1B0800 TO 0x1B0BFF EPAGE 1C: 0x1C0800 TO 0x1C0BFF EPAGE 1D: 0x1D0800 TO 0x1D0BFF EPAGE 1E: 0x1E0800 TO 0x1E0BFF EPAGE 1F: 0x1F0800 TO 0x1F0BFF 128K PFlash block 1 setup: PPAGE E0: 0xE08000 TO 0xE0BFFF PPAGE E1: 0xE18000 TO 0xE1BFFF PPAGE E2: 0xE28000 TO 0xE2BFFF PPAGE E3: 0xE38000 TO 0xE3BFFF PPAGE E4: 0xE48000 TO 0xE4BFFF PPAGE E5: 0xE58000 TO 0xE5BFFF PPAGE E6: 0xE68000 TO 0xE6BFFF PPAGE E7: 0xE78000 TO 0xE7BFFF 256K PFlash block 0 setup: PPAGE F0: 0xF08000 TO 0xF0BFFF PPAGE F1: 0xF18000 TO 0xF1BFFF PPAGE F2: 0xF28000 TO 0xF2BFFF PPAGE F3: 0xF38000 TO 0xF3BFFF PPAGE F4: 0xF48000 TO 0xF4BFFF PPAGE F5: 0xF58000 TO 0xF5BFFF PPAGE F6: 0xF68000 TO 0xF6BFFF PPAGE F7: 0xF78000 TO 0xF7BFFF PPAGE F8: 0xF88000 TO 0xF8BFFF PPAGE F9: 0xF98000 TO 0xF9BFFF PPAGE FA: 0xFA8000 TO 0xFABFFF PPAGE FB: 0xFB8000 TO 0xFBBFFF PPAGE FC: 0xFC8000 TO 0xFCBFFF PPAGE FE: 0xFE8000 TO 0xFEBFFF PPAGE FD: 0x004000 TO 0x007FFF PPAGE FF: 0x00C000 TO 0x00FFFF There are two security bits in the P-Flash Block 0. These bits (SEC01 SEC00) are Bit1 and Bit0 of address $FF0F in the Data Pattern. EEE Non-Volatile Information Register can be set under Device > Configure. Partition D-Flash option must be set to Yes under Device > Configure if DPART and EPART configure options are to be Programmed. Please make sure that the D-Flash data in the Data Pattern matches what is set as partitions (if used) under Device > Configure.

BPM does not sell programmable devices, nor do we program devices directly. BPM makes programmers and accessories to make programming in-house fast, easy, and profitable.

Additional information

Manufacturer

Freescale Semiconductor

Packages

QFP(112)

Part Number

MC9S12XEG384VAL

Set programming

Yes

Vcc(program)

5

Package