Freescale Semiconductor T1023NSE7PQAA BGA(525) Device
Adapters for Automated Programmers
| 8th Gen |
| FVEASM525BGA, FVEASM525BGA |
Adapters for Manual Programmers
| 8th Gen | 9th Gen |
| FVEASM525BGA, FVEASM525BGA | FVEASM525BGA |
Adapters for Engineering Programmers
Last Updated: 05/18/2023
If the device is not yet supported by your BPM programmer (Generation), request Device Support
Note
IMPORTANT:
| Device Type: | Communications processor (Power Architecture) |
| Device Size: | See below |
| Algorithm Programming Mode: | JTAG |
Memory Organization:
| Memory Type |
Attributes(*)
|
Included in default Range (Y/N) | DUT Physical Byte Address(hex)(if this area is selected/Activated) | BPWin Buffer Byte Address(hex) |
| SFP_INGR | R | Yes | FE0E_8020 – FE0E_8023 | E_8020 – E_8023 |
| SFP_SVHESR | R | Yes | FE0E_8024 – FE0E_8027 | E_8024 – E_8027 |
| SFP_SFPCR | R | Yes | FE0E_8028 – FE0E_802B | E_8028 – E_802B |
| SFP_VERSION | R | Yes | FE0E_8034 – FE0E_8037 | E_8034 – E_8037 |
| SFP_OSPR | R/W | Yes | FE0E_8200 – FE0E_8203 | E_8200 – E_8203 |
| SFP_DPR | R/W | Yes | FE0E_8208 – FE0E_820B | E_8208 – E_820B |
| SFP_DCVR0-SFP_DCVR1 | R/W | Yes | FE0E_820C – FE0E_8213 | E_820C – E_8213 |
| SFP_DRVR0-SFP_DRVR1 | W | Yes | FE0E_8214 – FE0E_821B | E_8214 – E_821B |
| SFP_OTPMKR0-SFP_OTPMKR7 | W | Yes | FE0E_821C – FE0E_823B | E_821C – E_823B |
| SFP_SRKHR0-SFP_SRKHR7 | R/W | Yes | FE0E_823C – FE0E_825B | E_823C – E_825B |
| Default Algorithm Range | — | — | FE0E_8020 – FE0E_825B | E_8020 – E_825B |
* R:Read only W: One time programmable (OTP) R/W: readable and one time programmable (OTP) R/W/E: readable and rewritable if not locked. Special Device Considerations:
| Option | Description | Default | Supported (Y/N)? |
| Debug Permissions (DP) | SFP_DPR(bits[29..31]) are used to set debug Permissions. 000: Level 0 (Open Mode) 001: Level 1 (Conditionally closed without notification mode) 01x: Level 2 (Conditionally closed with notification) 1xx: Level 3 (Closed). If DP is set to Level 1 or Level 2 Read Compare and Verify operations cannot be performed without having the programmed values of SFP_DRVR0-SFP_DRVR1. In this case values of SFP_DRVR0-SFP_DRVR1 must be set in corresponding buffer locations to perform Verify or set under Device–> Settings to perform Read/Compare. Otherwise data readback from the device is invalid. If DP protection is set to level 3 device debug interface is disabled. In this case WP bit in SFP_OSPR will be ignored during Program and all further operations on device will fail. | Level 0 | Yes |
| 1. | SFP_DRVR0-SFP_DRVR1 and SFP_OTPMKR0-SFP_OTPMKR7 cannot be read and hence will be ignored during Read Compare and Verify. | |
| 2. | Only SFP_OSPR SFP_DPR SFP_DCVR0-SFP_DCVR1 and SFP_SRKHR0-SFP_SRKHR7 will be checked during Verify and Compare operations. | |
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Additional information
| Manufacturer | Freescale Semiconductor |
|---|---|
| Packages | BGA(525) |
| Part Number | T1023NSE7PQAA |
| Set programming | Yes |
| Vcc(program) | 1.8 |
| 8-bit Bytes | |
| Package |