Infineon(Siemens) IRPS5401MTRPBF (Custom 01) QFN(56) Device
Adapters for Automated Programmers
| 6th Gen | 7th Gen | 9th Gen |
| FASMR56QFNK | FX4ASMR56QFNK, FASMR56QFNK, LX4ASMR56QFNK (repl.) | LX4ASMR56QFNK |
Adapters for Manual Programmers
| 6th Gen | 7th Gen | 9th Gen |
| FASMR56QFNK | FX4ASMR56QFNK, FASMR56QFNK, LX4ASMR56QFNK (repl.) | LX4ASMR56QFNK |
Adapters for Engineering Programmers
| 6th Gen | 7th Gen |
| FASMR56QFNK | FX4ASMR56QFNK, FASMR56QFNK, LX4ASMR56QFNK (repl.) |
Last Updated: 05/18/2023
If the device is not yet supported by your BPM programmer (Generation), request Device Support
Note
IMPORTANT:
| Device Type: | Infineon Flexible Power Management Unit |
| Device Memory Type: | Configuration Registers |
| Algorithm Programming Method: | PMBus |
| Supported Data File Format: | Multiple Image Configuration File (.mic) |
| Serialization Supported: | No |
Memory Organization:
| Memory Type |
Attributes(*) |
Included in Default Range (Y/N) | DUT PhysicalByte Address (hex) | BPWin BufferByte Address (hex) |
| Configuration Registers | R/W/E | Yes | 0000 – 17FF | Determined by data file |
| Default Algorithm Range | — | — | 0000 – 17FF | Determined by data file |
* R/W/E: readable and rewritable if not locked. Configuration Register Mapping:
| Section | Switcher | Register Range (hex) | Enable Register (hex) and Bit |
| CNFG | — | 0000 – 0001 | — |
| User | Common | 0020 – 003A | — |
| User | A | 0420 – 043F0600 – 06FF0700 – 07FF | 0038[0] |
| User | B | 0820 – 083F0A00 – 0AFF0B00 – 0BFF | 0038[1] |
| User | C | 0C20 – 0C3F0E00 – 0EFF0F00 – 0FFF | 0038[2] |
| User | D | 1020 – 103F1200 – 12FF1300 – 13FF | 0038[3] |
| User | LDO | 1420 – 143F1600 – 16FF1700 – 17FF | 0038[4] |
Special Device Considerations:
| 1. | Blank Check will check if any CNFG or User section writes have been performed. It is strongly recommended to leave Blank Check enabled. |
| 2. | The CNFG section is limited to five image writes.If Blank Check is disabled and there are no more write attempts the CNFG section will not re-program correctly. |
| 3. | The User section is limited to 26 image writes.This algorithm will program the User image number as specified in the data file. If Blank Check is disabled and a particular image has already been written the image will not re-program correctly. |
| 4. | The CNFG section should be programmed at least once.Otherwise the User section may not verify correctly. |
| 5. | This algorithm will only program and verify the register rangeslisted in the Configuration Register Mapping table above.The masks in the data file will determine which bits to verify. |
| 6. | By default all switcher registers will be verified. If register 0038h is specified in the data filethe data there will be used to determine which switcher registers to verify.See the Configuration Register Mapping table above for which bit corresponds to which switcher.A bit value of 0b will enable that switcher and 1b will disable it. |
| 7. | Operations on the TRIM section are not supported. |
| 8. | Check MTP operation checks how many writes are left in the USER/CNFG sections. |
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BPM does not sell programmable devices, nor do we program devices directly. BPM makes programmers and accessories to make programming in-house fast, easy, and profitable.
Additional information
| 8-bit Bytes | 1048576 |
|---|---|
| Manufacturer | Infineon(Siemens) |
| Packages | QFN(56) |
| Part Number | IRPS5401MTRPBF |
| Vcc(program) | 5 |
| Package |