Intel PC28F128P33T (Full Array Lock) BGA(64) Device

Adapters for Automated Programmers

6th Gen	7th Gen	9th Gen
FXASMR64BGB, FASMR64BGB	FX4ASMR64BGB, FXASMR64BGB, FASMR64BGB, LX4ASMR64BGB (repl.)	LX4ASMR64BGB

Adapters for Manual Programmers

6th Gen	7th Gen	9th Gen
FXSMR64BGB, FSMR64BGB, FXASMR64BGB, FASMR64BGB	FX4SMR64BGB, FXSMR64BGB, FSMR64BGB, FX4ASMR64BGB, FXASMR64BGB, FASMR64BGB, LX4ASMR64BGB (repl.)	LX4ASMR64BGB

Adapters for Engineering Programmers

6th Gen	7th Gen
FXSMR64BGB, FSMR64BGB, FXASMR64BGB, FASMR64BGB	FX4SMR64BGB, FXSMR64BGB, FSMR64BGB, FX4ASMR64BGB, FXASMR64BGB, FASMR64BGB, LX4ASMR64BGB (repl.)

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Last Updated: 05/18/2023

IMPORTANT: This Algorithm is only for the device with FAL(Full Array Protection Locking) security feature. All Main Blocks can be locked permanently by programming the corresponding bit located in Buffer. This is an OTP operation.

OTP Address(1)	Data Pattern Address	Main Array Blocks Protected
ECh	10000D5h-10000D4h	112:130(2)
EDh	10000D7h-10000D6h	96:111
F0h	10000DDh-10000DCh	80:95
F1h	10000DFh-10000DEh	64:79
F4h	10000E5h-10000E4h	48:63
F5h	10000E7h-10000E6h	32:47
F8h	10000EDh-10000ECh	16:31
F9h	10000EFh-10000EEh	0:15

Notes: 1. For Top Boot the highest number OTP bit locks the lowest numbered block.For example programming bit 15 of OTP address F1h permanently locks Block 64and bit 0 permanently locks Block 79. 2. Programming bit 0 of Device Address ECh (Data Pattern Address 10000D4h) locks four parameter blocks(Blocks 127-130). 128Mbit (8M x 16) Intel StrataFlash(R) Memory. This device contains 17 128-bit Protection Registers PR0 through PR16 located at address range [1000000h-1000007h] in the Data Pattern. Example: PR0[0x81-0x88] is located at [1000000h-100000Fh] PR1[0x8A-0x91] at [1000010h-100010Fh] and so on. PR0[63:0] are permanently programmed by Intel with a unique number for each flash device. PR0[127:64] and PR1 through PR16 are one-time programmable (OTP) and available for the user to program. If one or more OTP registers are programmed the range must be set to exclude the registers or Erase/Program will fail. Once programmed the user-programmable register can be locked to prevent further programming using Device > Configure menu. Once the protection register is locked the entire user segment is locked and no more user bits may be programmed. The default Device Range is set to [000000h-7FFFFFh]. Please select ‘Entire File’ under Device > Range if Protection Registers need to be included. ‘