Intel PC28F512P33BF BGA(64) Device

Adapters for Automated Programmers

6th Gen	7th Gen	9th Gen
FXASMR64BGB, FASMR64BGB	FX4ASMR64BGB, FXASMR64BGB, FASMR64BGB, LX4ASMR64BGB (repl.)	LX4ASMR64BGB

Adapters for Manual Programmers

6th Gen	7th Gen	9th Gen
FXSMR64BGB, FSMR64BGB, FXASMR64BGB, FASMR64BGB	FX4SMR64BGB, FXSMR64BGB, FSMR64BGB, FX4ASMR64BGB, FXASMR64BGB, FASMR64BGB, LX4ASMR64BGB (repl.)	LX4ASMR64BGB

Adapters for Engineering Programmers

6th Gen	7th Gen
FXSMR64BGB, FSMR64BGB, FXASMR64BGB, FASMR64BGB	FX4SMR64BGB, FXSMR64BGB, FSMR64BGB, FX4ASMR64BGB, FXASMR64BGB, FASMR64BGB, LX4ASMR64BGB (repl.)

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Last Updated: 05/18/2023

IMPORTANT: 512Mbit (32M x 16) Memory. This device contains 17 128-bit Protection Registers PR0 through PR16 located at address range [4000000h-400010Fh] in the Data Pattern. Example: PR0[0x81-0x88] is located at [4000000h-400000Fh] PR1[0x8A-0x91] at [4000010h-400001Fh] and so on. PR0[63:0] are permanently programmed by Intel with a unique number for each flash device. PR0[127:64] and PR1 through PR16 are one-time programmable (OTP) and available for the user to program. Once programmed the user-programmable register can be locked to prevent further programming using Device > Configure menu. Once the protection register is locked the entire user segment is locked and no more user bits may be programmed. One Time Protection is available in 3 different customer ordered options. The option information is only available on the packaging of the device and is not marked on the device itself. Device operation will fail ‘Initialize’ under the following conditions: 1.’Simple OTP’ or ‘Device OTP’ option is selected under Device > Configure for a ‘Standard OTP’ device. 2.’Standard OTP’ option is selected under Device > Configure for a ‘Simple OTP’ or ‘Device OTP’ device. The first option-‘Standard OTP’ does not allow any special OTP protection of the main array. The second option-‘Simple OTP’ allows up to 512KB of Main Memory OTP protection. This option pre-defines 512KB of the main array that includes the 4×32 KB parameter blocks ganged together as one block and the adjacent 3×128 KB main blocks. Please set the bit according to the main block needed to be protected under Device > Configure:

Lock Register 0	Block Protected
Bit 2	Blocks 3:0(parameters)
Bit 3	Block 4(main)
Bit 4	Block 5(main)
Bit 5	Block 6(main)
Bit 6	Lock Bits 2-5

The third option-‘Device OTP’ will allow protection of data in all of the main memory array blocks.

OTP Address(1)	Data Pattern Address	Main Array Blocks Protected
ECh	40000D5h-40000D4h	18:0(2)
EDh	40000D7h-40000D6h	34:19
F0h	40000DDh-40000DCh	50:35
F1h	40000DFh-40000DEh	66:51
F4h	40000E5h-40000E4h	82:67
F5h	40000E7h-40000E6h	98:83
F8h	40000EDh-40000ECh	114:99
F9h	40000EFh-40000EEh	130:115
FCh	40000F5h-40000F4h	146:131
FDh	40000F7h-40000F6h	162:147
100h	40000FDh-40000FCh	178:163
101h	40000FFh-40000FEh	194:179
104h	4000105h-4000104h	210:195
105h	4000107h-4000106h	226:211
108h	400010Dh-400010Ch	242:227
109h	400010Fh-400010Eh	258:243

Notes: 1. For Bottom Boot the highest number OTP bit locks the highest numbered block.For example programming bit 15 of OTP address F1h permanently locks Block 66and bit 0 permanently locks Block 51. 2. Programming bit 0 of Device Address ECh (Data Pattern Address 40000D4h) locks four parameter blocks(Blocks 0-3). The default Device Range is set to [000000h-1FFFFFF]. Please select ‘Entire File’ under Device > Range if Protection Registers need to be included. Password Access Feature is currently not supported. ‘