Intel RC48F4400P0TB0E BGA(64) Device
Adapters for Automated Programmers
| 6th Gen | 7th Gen | 9th Gen |
| FXASMR64EBGI, FXASM64EBGI, FASMR64EBGI, FASM64EBGI, FXASM64EBGC, FXASM64EBGA, FASM64EBGC, FASM64EBGA | FX4ASMR64EBGI, FX4ASM64EBGI, FXASMR64EBGI, FXASM64EBGI, FASMR64EBGI, FASM64EBGI, FXASM64EBGC, FXASM64EBGA, FASM64EBGC, FASM64EBGA, WX4ASM64EBGI (repl.), LX4ASMR64EBGI (repl.) | WX4ASM64EBGI, LX4ASMR64EBGI |
Adapters for Manual Programmers
| 6th Gen | 7th Gen | 9th Gen |
| FXSMR64EBGI, FXSM64EBGI, FSMR64EBGI, FSM64EBGI, FXSM64EBGC, FXSM64EBGA, FSM64EBGC, FSM64EBGA, FXASMR64EBGI, FXASM64EBGI, FASMR64EBGI, FASM64EBGI, FXASM64EBGC, FXASM64EBGA, FASM64EBGC, FASM64EBGA | FX4SMR64EBGI, FX4SM64EBGI, FXSMR64EBGI, FXSM64EBGI, FSMR64EBGI, FSM64EBGI, FXSM64EBGC, FXSM64EBGA, FSM64EBGC, FSM64EBGA, FX4ASMR64EBGI, FX4ASM64EBGI, FXASMR64EBGI, FXASM64EBGI, FASMR64EBGI, FASM64EBGI, FXASM64EBGC, FXASM64EBGA, FASM64EBGC, FASM64EBGA, WX4ASM64EBGI (repl.), LX4ASMR64EBGI (repl.) | WX4ASM64EBGI, LX4ASMR64EBGI |
Adapters for Engineering Programmers
| 6th Gen | 7th Gen |
| FXSMR64EBGI, FXSM64EBGI, FSMR64EBGI, FSM64EBGI, FXSM64EBGC, FXSM64EBGA, FSM64EBGC, FSM64EBGA, FXASMR64EBGI, FXASM64EBGI, FASMR64EBGI, FASM64EBGI, FXASM64EBGC, FXASM64EBGA, FASM64EBGC, FASM64EBGA | FX4SMR64EBGI, FX4SM64EBGI, FXSMR64EBGI, FXSM64EBGI, FSMR64EBGI, FSM64EBGI, FXSM64EBGC, FXSM64EBGA, FSM64EBGC, FSM64EBGA, FX4ASMR64EBGI, FX4ASM64EBGI, FXASMR64EBGI, FXASM64EBGI, FASMR64EBGI, FASM64EBGI, FXASM64EBGC, FXASM64EBGA, FASM64EBGC, FASM64EBGA, WX4ASM64EBGI (repl.), LX4ASMR64EBGI (repl.) |
Last Updated: 05/18/2023
If the device is not yet supported by your BPM programmer (Generation), request Device Support
Note
IMPORTANT: Intel StrataFlash(R) Embedded Memory System. This device contains one bottom boot code segment flash die and one top boot data segment flash die. Device contains 34 128-bit Protection Registers Flash 1 PR0 through PR16 located at address range [4000000h-400010Fh] in the buffer. Example: Flash 1 PR0[0x81-0x88] is located at [4000000h-400000Fh] Flash 1 PR1[0x8A-0x91] at [4000010h-400001Fh] and so on. Flash 1 PR0[63:0] are permanently programmed by Intel with a unique number for each flash device. Flash 1 PR0[127:64] and PR1 through PR16 are one-time programmable (OTP) and available for user to program. Flash 2 PR0 through PR16 located at address range [4000110h-400021Fh] in the buffer. Example: Flash 2 PR0[0x81-0x88] is located at [4000110h-400011Fh] Flash 2 PR1[0x8A-0x91] at [4000120h-400012Fh] and so on. Flash 2 PR0[63:0] are permanently programmed by Intel with a unique number for each flash device. Flash 2 PR0[127:64] and PR1 through PR16 are one-time programmable (OTP) and available for user to program. If one or more OTP registers are programmed the range must be set to exclude the registers or the ERASE command will fail. Once programmed the user-programmable register can be locked to prevent further programming using Device > Configure menu. Once the protection register is locked the entire user segment is locked and no more user bits may be programmed. Notes: 1. For Bottom Boot the highest number OTP bit locks the highest numbered block.For example programming bit 15 of OTP address F1h permanently locks Block 66and bit 0 permanently locks Block 51. 2. Programming bit 0 of Device Address ECh (Data Pattern Address 40000D4h) locks four parameter blocks(Blocks 0-3). 3. Programming bit 0 of Device Address ECh (Data Pattern Address 40001E4h) locks four parameter blocks(Blocks 514-517). The default Device Range is set to [0000000h-1FFFFFFh]. Please select Entire File’ under Device Range if Protection Registers need to be included. ‘
BPM does not sell programmable devices, nor do we program devices directly. BPM makes programmers and accessories to make programming in-house fast, easy, and profitable.
Additional information
| Manufacturer | Intel |
|---|---|
| Packages | BGA(64) |
| Part Number | RC48F4400P0TB0E |
| Set programming | Yes |
| Vcc(program) | 3.3 |
| Package |