Lattice L-ASC10-1SG48I QFN(48) Device
Adapters for Automated Programmers
| 8th Gen | 9th Gen |
| FVE4ASM48QFNXJ, FVE4ASM48QFNXJ | LX4ASMR48QFNXJ |
Adapters for Manual Programmers
| 8th Gen | 9th Gen |
| FVE4ASM48QFNXJ, FVE4ASM48QFNXJ | LX4ASMR48QFNXJ |
Adapters for Engineering Programmers
Last Updated: 05/18/2023
If the device is not yet supported by your BPM programmer (Generation), request Device Support
Note
IMPORTANT:
| Device Type: | In-System Programmable Hardware Management Expander. |
| Algorithm Programming Method: | I2C. |
Memory Organization:
| Memory Type |
Attributes(*)
|
Included in default Range (Y/N) | DUT Physical Byte Address(hex)(if this area is selected/Activated) | BPWin Buffer Byte Address(hex) | EEPROM for device configuration. | R/W | Yes | 00 – 77 | 00 – 77 |
| Default Algorithm Range | — | — | 00 – 77 | 00 – 77 |
* R:Read only W: One time programmable (OTP) R/W: readable and one time programmable (OTP) R/W/E: readable and rewritable if not locked. Any configurations listed under Device-Specific’ in the menu item Device-> Settings will be written to the DUT during ‘Program’ operation. Special Device Considerations: Data file must be loaded as type ‘Straight’. The 16-bit CRC (addresses 72h-73h in Data Pattern) is ignored. The 3 LSB bits in ASC address (address 0h in Data Pattern) is ignored in program and verify. Serialization is not supported by this algorithm. ‘
BPM does not sell programmable devices, nor do we program devices directly. BPM makes programmers and accessories to make programming in-house fast, easy, and profitable.
Additional information
| 8-bit Bytes | 120 |
|---|---|
| Manufacturer | Lattice |
| Packages | QFN(48) |
| Part Number | L-ASC10-1SG48I |
| Vcc(program) | 3.3 |
| Package |