Microchip Technology PIC24FJ128GB106-I/PT QFP(64) Device
Adapters for Automated Programmers
| 6th Gen | 7th Gen | 9th Gen |
| FASMR64QPT, FASM64QAJ, FASM64PQTM, FASM64PQTF, FASM64PQTX, FASM64PQT, FASM64PQTA, LASMR64QPT (repl.) | FASMR64QPT, FASM64QAJ, FASM64PQTM, FASM64PQTF, FASM64PQTX, FASM64PQT, FASM64PQTA, LASMR64QPT (repl.) | LASMR64QPT |
Adapters for Manual Programmers
| 6th Gen | 7th Gen | 9th Gen |
| FSM64PQTA, FASMR64QPT, FSM64QAJ, FSM64PQTM, FSM64PQTF, FSM64PQTX, FSM64PQT, FASM64QAJ, FASM64PQTM, FASM64PQTF, FASM64PQTX, FASM64PQT, FASM64PQTA, LASMR64QPT (repl.) | FSM64PQTA, FASMR64QPT, FSM64QAJ, FSM64PQTM, FSM64PQTF, FSM64PQTX, FSM64PQT, FASM64QAJ, FASM64PQTM, FASM64PQTF, FASM64PQTX, FASM64PQT, FASM64PQTA, LASMR64QPT (repl.), FSM64PQTA, FASMR64QPT, FSM64QAJ, FSM64PQTM, FSM64PQTF, FSM64PQT, FSM64PQTX, FASM64QAJ, FASM64PQTM, FASM64PQTF, FASM64PQT, FASM64PQTX, FASM64PQTA, LASMR64QPT (repl.) | LASMR64QPT |
Adapters for Engineering Programmers
| 6th Gen | 7th Gen |
| FSM64PQTA, FASMR64QPT, FSM64QAJ, FSM64PQTM, FSM64PQTF, FSM64PQTX, FSM64PQT, FASM64QAJ, FASM64PQTM, FASM64PQTF, FASM64PQTX, FASM64PQT, FASM64PQTA, LASMR64QPT (repl.) | FSM64PQTA, FASMR64QPT, FSM64QAJ, FSM64PQTM, FSM64PQTF, FSM64PQTX, FSM64PQT, FASM64QAJ, FASM64PQTM, FASM64PQTF, FASM64PQTX, FASM64PQT, FASM64PQTA, LASMR64QPT (repl.) |
Last Updated: 05/18/2023
If the device is not yet supported by your BPM programmer (Generation), request Device Support
Note
IMPORTANT: Please perform Program’ operation first if the Programming Executive’s prensence is unknown. Microcontroller with User Flash Code Memory (87Kx24-bit) The Code Memory is a 24 bit memory addressed from [0h-2AFFFh] in the Data Pattern. The three configuration words(3×24-bit) are addressed in the Data Pattern at [2AFF4h-2AFFFh]. The Code Memory(including configuration words) is a 24-bit value on a 32-bit boundary. This algorithm assumes Little Endian format for programming data. Please set ‘Little Endian’ under Device->Byte Order. ERASE will erase the entire memory including executive memory. The Configuration words may be set from Device Configure or from the above mentioned addresses in the Buffer. Please use help notes in the Device Configure to view more information about bit identities and reserved bit locations or see Microchip specifications. Sum operation does not use Microchip specific sum calculation. If GCP bit (in 157FEh Flash Configuration Words) is set to ‘0’ Code Memory Space will be locked. Attempt to do stand alone Verify/Compare will result a failure. GCP bit can be reset by performing Erase operation ‘
BPM does not sell programmable devices, nor do we program devices directly. BPM makes programmers and accessories to make programming in-house fast, easy, and profitable.
Additional information
| Manufacturer | Microchip Technology |
|---|---|
| Packages | QFP(64) |
| Part Number | PIC24FJ128GB106-I/PT |
| Vcc(program) | 3.3 |
| Package |