Micron MT29F2G08ABAEAWP:E (Custom01) TSOP(48) Device
Adapters for Automated Programmers
| 8th Gen | 9th Gen | Flashstream |
| FVE4ASMR48TNL, FVE4ASM48TNL, FVE4ASMR48TN, FVE4ASM48TN, FVE4ASMR48TNL, FVE4ASMR48TN, FVE4ASM48TN, FVE4ASM48TNL | FVE4ASMR48TNL, FVE4ASMR48TN, FVE4ASM48TN, FVE4ASM48TNL | FVE4ASMR48TNL, FVE4ASM48TNL, FVE4ASMR48TN, FVE4ASM48TN, FVE4ASMR48TNL, FVE4ASMR48TN, FVE4ASM48TN, FVE4ASM48TNL |
Adapters for Manual Programmers
| 8th Gen | 9th Gen | Flashstream |
| FVE4ASMR48TNL, FVE4ASM48TNL, FVE4ASMR48TN, FVE4ASM48TN, FVE4ASMR48TNL, FVE4ASMR48TN, FVE4ASM48TN, FVE4ASM48TNL | FVE4ASMR48TNL, FVE4ASMR48TN, FVE4ASM48TN, FVE4ASM48TNL | FVE4ASMR48TNL, FVE4ASM48TNL, FVE4ASMR48TN, FVE4ASM48TN, FVE4ASMR48TNL, FVE4ASMR48TN, FVE4ASM48TN, FVE4ASM48TNL |
Adapters for Engineering Programmers
Last Updated: 05/18/2023
If the device is not yet supported by your BPM programmer (Generation), request Device Support
Note
IMPORTANT: This is a custom algorithm. This algorithm program only devices that have two bad blocks (block 100 and block 101). This is a NAND Flash Memory device with a minimum of 2008 blocks. Each block contains 64 pages which are divided into a 2K Byte main page and a 64 byte control area. This algorithm is mapped with each page considered a contiguous (2K+64) byte page. Bad Blocks are indicated at byte 2048 of the first page of a block. This device uses an internal ECC that is supported under Device Config -> Settings. If enabled please deselect the ‘Include Spare Area’ box in Device Config -> NAND Options. Bit Error Rate Tolerance is set to ‘1’ by default. It can be modified under Device > NAND Options. ‘
BPM does not sell programmable devices, nor do we program devices directly. BPM makes programmers and accessories to make programming in-house fast, easy, and profitable.
Additional information
| 8-bit Bytes | 276824064 |
|---|---|
| Manufacturer | Micron |
| Packages | TSOP(48) |
| Part Number | MT29F2G08ABAEAWP:E |
| Vcc(program) | 3.3 |
| Package |