Numonyx PC28F640P30TF BGA(64) Device

Adapters for Automated Programmers

6th Gen	7th Gen
FXASMR64EBGI, FXASM64EBGI, FASMR64EBGI, FASM64EBGI, FXASM64EBGC, FXASM64EBGA, FASM64EBGC, FASM64EBGA	FX4ASMR64EBGI, FX4ASM64EBGI, FXASMR64EBGI, FXASM64EBGI, FASMR64EBGI, FASM64EBGI, FXASM64EBGC, FXASM64EBGA, FASM64EBGC, FASM64EBGA

Adapters for Manual Programmers

6th Gen	7th Gen
FXSMR64EBGI, FXSM64EBGI, FSMR64EBGI, FSM64EBGI, FXSM64EBGC, FXSM64EBGA, FSM64EBGC, FSM64EBGA, FXASMR64EBGI, FXASM64EBGI, FASMR64EBGI, FASM64EBGI, FXASM64EBGC, FXASM64EBGA, FASM64EBGC, FASM64EBGA	FX4SMR64EBGI, FX4SM64EBGI, FXSMR64EBGI, FXSM64EBGI, FSMR64EBGI, FSM64EBGI, FXSM64EBGC, FXSM64EBGA, FSM64EBGC, FSM64EBGA, FX4ASMR64EBGI, FX4ASM64EBGI, FXASMR64EBGI, FXASM64EBGI, FASMR64EBGI, FASM64EBGI, FXASM64EBGC, FXASM64EBGA, FASM64EBGC, FASM64EBGA, WX4ASM64EBGI (repl.), LX4ASMR64EBGI (repl.)

Adapters for Engineering Programmers

6th Gen	7th Gen
FXSMR64EBGI, FXSM64EBGI, FSMR64EBGI, FSM64EBGI, FXSM64EBGC, FXSM64EBGA, FSM64EBGC, FSM64EBGA, FXASMR64EBGI, FXASM64EBGI, FASMR64EBGI, FASM64EBGI, FXASM64EBGC, FXASM64EBGA, FASM64EBGC, FASM64EBGA	FX4SMR64EBGI, FX4SM64EBGI, FXSMR64EBGI, FXSM64EBGI, FSMR64EBGI, FSM64EBGI, FXSM64EBGC, FXSM64EBGA, FSM64EBGC, FSM64EBGA, FX4ASMR64EBGI, FX4ASM64EBGI, FXASMR64EBGI, FXASM64EBGI, FASMR64EBGI, FASM64EBGI, FXASM64EBGC, FXASM64EBGA, FASM64EBGC, FASM64EBGA, WX4ASM64EBGI (repl.), LX4ASMR64EBGI (repl.)

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Last Updated: 05/18/2023

IMPORTANT: 64Mbit Flash. This device contains 17 128-bit Protection Registers PR0 through PR16 located at address range [800000h-80010Fh] in the Data Pattern. Example: PR0[0x81-0x88] is located at [800000h-80000Fh] PR1[0x8A-0x91] at [800010h-80001Fh] and so on. PR0[63:0] are permanently programmed by Intel with a unique number for each flash device. PR0[127:64] and PR1 through PR16 are one-time programmable (OTP) and available for the user to program. Once programmed the user-programmable register can be locked to prevent further programming using Device > Configure menu. Once the protection register is locked the entire user segment is locked and no more user bits may be programmed. One Time Protection is available in 3 different customer ordered options. The option information is only available on the packaging of the device and is not marked on the device itself. Device operation will fail ‘Initialize’ under the following conditions: 1.’Simple OTP’ or ‘Device OTP’ option is selected under Device > Configure for a ‘Standard OTP’ device. 2.’Standard OTP’ option is selected under Device > Configure for a ‘Simple OTP’ or ‘Device OTP’ device. The first option-‘Standard OTP’ does not allow any special OTP protection of the main array. The second option-‘Simple OTP’ allows up to 512KB of Main Memory OTP protection. This option pre-defines 512KB of the main array that includes the 4×32 KB parameter blocks ganged together as one block and the adjacent 3×128 KB main blocks. Please set the bit according to the main block needed to be protected under Device > Configure:

Lock Register 0	Block Protected
Bit 2	Blocks 66:63(parameters)
Bit 3	Block 62(main)
Bit 4	Block 61(main)
Bit 5	Block 60(main)
Bit 6	Lock Bits 2-5

The third option-‘Device OTP’ will allow protection of data in all of the main memory array blocks.

OTP Address(1)	Data Pattern Address	Main Array Blocks Protected
ECh	8000D5h-8000D4h	48:66(2)
EDh	8000D7h-8000D6h	32:47
F0h	8000DDh-8000DCh	16:31
F1h	8000DFh-8000DEh	0:15

Notes: 1. For Top Boot the highest number OTP bit locks the lowest numbered block.For example programming bit 15 of OTP address F1h permanently locks Block 0and bit 0 permanently locks Block 15. 2. Programming bit 0 of Device Address ECh (Data Pattern Address 8000D4h) locks four parameter blocks(Blocks 63-66). The default Device Range is set to [000000h-3FFFFFh]. Please select ‘Entire File’ under Device > Range if Protection Registers need to be included. Password Access Feature is currently not supported. ‘