NXP Semiconductors LPC2388FBD144 QFP(144) Device

Adapters for Automated Programmers

6th Gen	7th Gen	8th Gen	9th Gen
FASMR144LQFA	FX2ASMR144LQFA, FASMR144LQFA	FVE2ASMR144QFPK, FVE2ASMR144QFPK	FVE2ASMR144QFPK

Adapters for Manual Programmers

6th Gen	7th Gen	8th Gen	9th Gen
FSMR144LQFA, FASMR144LQFA	FX2SMR144LQFA, FSMR144LQFA, FX2ASMR144LQFA, FASMR144LQFA, LX2ASMR144LQFA (repl.)	FVE2ASMR144QFPK, FVE2ASMR144QFPK	FVE2ASMR144QFPK

Adapters for Engineering Programmers

6th Gen	7th Gen
FSMR144LQFA, FASMR144LQFA	FX2SMR144LQFA, FSMR144LQFA, FX2ASMR144LQFA, FASMR144LQFA, LX2ASMR144LQFA (repl.)

Last Updated: 05/18/2023

If the device is not yet supported by your BPM programmer (Generation), request Device Support

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Note

IMPORTANT:

Device Type:	Microcontroller with Flash Memory
Device Size:	512KB
Algorithm Programming method:	JTAG

Memory Organization:

Memory Type	*Attributes^()**	Included in default Range (Y/N)	DUT Physical Byte Address(hex)(if this area is selected/Activated)	BPWin Buffer Byte Address(hex)
Main Flash Area	R/W/E	Yes	0h-7DFFFh	0h-7DFFFh
Default Algorithm Range	—	—	0h-7DFFFh	0h-7DFFFh

* R:Read only W:One time programmable (OTP) R/W:readable and one time programmable (OTP) R/W/E:readable and rewritable if not locked. Any configurations listed under Device-Specific’ in the menu item Device-> Settings will be written to the DUT during ‘Program’ operation regardless of memory range selection. Special Device Considerations:

Device Configure option ‘Auto-run code in Flash after reset’ can be set to change buffer location 14h to contain the 2’s complement of the check-sum of the remaining interrupt vectors. Code read protection available under Device Configure is enabled by programming the flash address location 1FCh (User flash sector 0). It works in conjunction with the following values: CRP1 is enabled if value 12345678h(305419896 Decimal) is programmed. Access to chip via the JTAG pins is disabled. CRP2 is enabled if value 87654321h(2271560481 Decimal) is programmed. Access to chip via JTAG pins is disabled. The following ISP commands are also disabled: Read MemoryWrite to RAMGoCopy RAM to flash and Compare.ISP erase command only allows erasure of all user sectors. CRP3 is enabled if value 43218765h(1126270821 Decimal) is programmed. Access to chip via the JTAG pins is disabled. ISP entry by pulling P2.10 LOW is disabled if a valid user code is present in flash sector 0. When this mode is invoked no future factory testing can be performed on the device.

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BPM does not sell programmable devices, nor do we program devices directly. BPM makes programmers and accessories to make programming in-house fast, easy, and profitable.

More Info

Additional information

8-bit Bytes	516096
Manufacturer	NXP Semiconductors
Packages	QFP(144)
Part Number	LPC2388FBD144
Vcc(program)	3.3
Package