Philips Semiconductors LPC1758FBD80 QFP(80) Device

Adapters for Automated Programmers

6th Gen	7th Gen	9th Gen
FASM80LQFQ	FX4ASM80LQFQ, FASM80LQFQ, LX4ASM80LQFQ (repl.)	LX4ASM80LQFQ

Adapters for Manual Programmers

6th Gen	7th Gen	9th Gen
FSM80LQFQ, FASM80LQFQ	FX4SM80LQFQ, FSM80LQFQ, FX4ASM80LQFQ, FASM80LQFQ, LX4ASM80LQFQ (repl.)	LX4ASM80LQFQ

Adapters for Engineering Programmers

6th Gen	7th Gen
FSM80LQFQ, FASM80LQFQ	FX4SM80LQFQ, FSM80LQFQ, FX4ASM80LQFQ, FASM80LQFQ, LX4ASM80LQFQ (repl.)

Last Updated: 05/18/2023

If the device is not yet supported by your BPM programmer (Generation), request Device Support

Request Support Options

Note

IMPORTANT:

Device Type:	ARM Cortex-M3 based MCU
Device Size:	512 Kbyte

Memory Organization:

Memory Type	*Attributes^()**	Included in default Range (Y/N)	DUT Physical Byte Address(hex)(if this area is selected/Activated)	BPWin Buffer Byte Address(hex)
On Chip Flash	R/W/E	Yes	00000-7FFFF	00000-7FFFF

Default Algorithm Range	—	—	00000 – 7FFFF	00000 – 7FFFF

* R:Read only W:One time programmable (OTP) R/W:readable and one time programmable (OTP) R/W/E:readable and rewritable if not locked. Any configurations listed under Device-Specific’ in the menu item Device-> Settings will be written to the DUT during ‘Program’ operation regardless of memory range selection. Special Device Considerations:

Device Configure option ‘Auto-run code in Flash after reset’ can be set to change buffer location 1Chto contain the 2’s complement of the check-sum of the remaining interrupt vectors.Code read protection available under Device Configure is enabled by programmingthe flash address location 2FCh (User flash sector 0).It works in conjunction with the following values (Little Endian Byte Format):CRP1 is enabled if value 12345678h (305419896 Decimal) is programmed.Access to chip via the JTAG pins is disabled.CRP2 is enabled if value 87654321h (2271560481 Decimal) is programmed.Access to chip via JTAG pins is disabled. The following ISP commands are also disabled:Read Memory Write to RAM Go Copy RAM to flash and Compare.ISP erase command only allows erasure of all user sectors.CRP3 is enabled if value 43218765h (1126270821 Decimal) is programmed.Access to chip via the JTAG pins is disabled.ISP entry by pulling P2.10 LOW is disabled if a valid user code is present in flash sector 0.When this mode is invoked no future factory testing can be performed on the device.

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BPM does not sell programmable devices, nor do we program devices directly. BPM makes programmers and accessories to make programming in-house fast, easy, and profitable.

More Info

Additional information

8-bit Bytes	524288
Manufacturer	Philips Semiconductors
Packages	QFP(80)
Part Number	LPC1758FBD80
Vcc(program)	3.3
Package