STMicroelectronics STM32L053R8T6D LQFP(64) Device
Adapters for Automated Programmers
| 6th Gen | 7th Gen | 9th Gen |
| FASMR64LQFP | FX4ASMR64LQFP, FASMR64LQFP, LASMR64LQFP (repl.) | LASMR64LQFP |
Adapters for Manual Programmers
| 6th Gen | 7th Gen | 9th Gen |
| FSMR64LQFP, FASMR64LQFP | FX4SMR64LQFP, FSMR64LQFP, FX4ASMR64LQFP, FASMR64LQFP, LASMR64LQFP (repl.) | LASMR64LQFP |
Adapters for Engineering Programmers
| 6th Gen | 7th Gen |
| FSMR64LQFP, FASMR64LQFP | FX4SMR64LQFP, FSMR64LQFP, FX4ASMR64LQFP, FASMR64LQFP, LASMR64LQFP (repl.) |
Last Updated: 05/18/2023
If the device is not yet supported by your BPM programmer (Generation), request Device Support
Note
IMPORTANT:
| Device Type: | ARM 32-bit Cortex-M0+ CPU core |
| Device Size: | 64 Kbyte Flash Memory + 2Kbyte Data EEPROM |
| Algorithm Programming Method: | SWD + Custom bootloader |
Memory Organization:
| Memory Type |
Attributes(*)
|
Included in default Range (Y/N) | DUT Physical Byte Address(hex)(if this area is selected/Activated) | BPWin Buffer Byte Address(hex) |
| Flash Memory | R/W/E | Yes | 0800_0000 – 0800_FFFF | 0800_0000 – 0800_FFFF |
| Data EEPROM | R/W/E | No | 0808_0000 – 0808_07FF | 0808_0000 – 0808_07FF |
| User Option Bytes | R/W/E | No | 1FF8_0000 – 1FF8_001F | 1FF8_0000 – 1FF8_001F |
| Default Algorithm Range | — | — | 0800_0000 – 0800_FFFF | 0800_0000 – 0800_FFFF |
* R:Read only W: One time programmable (OTP) R/W: readable and one time programmable (OTP) R/W/E: readable and rewritable if not locked. Any configurations listed under Device-Specific’ in the menu item Device-> Settings will be written to the DUT during ‘Program’ operation. Special Device Considerations:
| Data Pattern Address | Bits [15:8] | Bits[7:0] |
| 1FFFF800h | nFLASH_OPTR[15:0] | FLASH_OPTR[15:0] |
| 1FFFF804h | nFLASH_OPTR[31:16] | FLASH_OPTR[31:16] |
| 1FFFF808h | nFLASH_WRPROT1[15:0] | FLASH_WRPROT1[15:0] |
| 1FFFF80Ch | nFLASH_WRPROT1[31:16] | FLASH_WRPROT1[31:16] |
| 1FFFF810h | nFLASH_WRPROT2[15:0] | FLASH_WRPROT2[15:0] |
1) If RDPROT option (FLASH_OPTR[7:0]) is set to level 1(None AAh Non CCh) the main Flash memory and the backup registers (RTC_BKPxR in the RTC) are totally inaccessible. 2) If RDPROT is set to level 2(CCh) device debug interface is disabled. Any operation on device fails. 3) If BOOT1 option bit (FLASH_OPTR[31]) is set to ‘0’ device will not be accessible by this algorithm. 4) A level 1 read protected or write protected device must be erased before it is programmed. Option bytes contain read and write protection bits and are always erased before program if selected. ‘
BPM does not sell programmable devices, nor do we program devices directly. BPM makes programmers and accessories to make programming in-house fast, easy, and profitable.
Additional information
| 8-bit Bytes | 536346656 |
|---|---|
| Manufacturer | STMicroelectronics |
| Packages | LQFP(64) |
| Part Number | STM32L053R8T6D |
| Set programming | Yes |
| Vcc(program) | 3.3 |
| Package |